Conventionally, test vectors are prevalently employed to screen out the unqualified chips. Since the parameters, such as the frequency, phase and duty cycle, of the clock inputted from a tester into the chip are precisely controlled, a specific test vector inputted into a normal chip is supposed to be outputted as expected. In other words, when the output of the chip in response to the specific test vector shows an unexpected result, the chip is determined to be an unqualified chip and should be ruled out.
Presently, a phase-locked loop (PLL) circuit is usually embedded in the chip for providing the clock signals of all required frequencies for the chip, thereby reducing the cost. Since the clock signal generated by the embedded PLL circuit is not a pure digital signal and its phase delay is unpredictable, there has been no specific test vectors, so far, and corresponding outputs for the embedded PLL circuit to perform test. Therefore, the embedded PLL circuit is not particularly tested in the prior art.
Therefore, the purpose of the present invention is to develop a circuit and a method for testing an embedded phase-locked loop (PLL) circuit to deal with the above situations encountered in the prior art.